
The hardware platform can be created/edited in CCSv6:
-Open the debug perspective
-From the menu, select Tools->RTSC Tools->Platform->Edit/View
-Select the package: kHwDm647
-Select the CPU Core: CPU
-Click Next to edit.

Settings need to be chosen to follow this rationale (from BIOS-5.x kHwDm647.tcf)

  We use a portion of L2 SRAM for static code/data (64K, allocated here) and another portion for a "fast heap" (64K, 
  allocated in kHwMemory). These resources are used mainly to minimize interrupt duration and latency.
 
  As in FS5, the L2 SRAM that we are using here is not documented in the DM647 datasheet (it's in the DM648 datasheet, 
  and seems to work in DM647, for now). We have found that there is a total of 256K of undocumented SRAM available on DM647
  (0x00A40000 - 0x00A7FFFF).

  If this undocumented feature is silently removed in future, one option would be to stop allocating SRAM for fast code/heap, 
  and use DDR2 instead. This would have a negative effect on ISR performance under heavy DDR2 traffic. 

  We have limited ourselves to using only 128K of this undocumented resource, to ensure that we have another option: 
  give up half of our 256K cache allocation.  This would also impact performance, but might be preferable (unknown). 
